1. Field of the Invention
The present invention relates to an interface circuit provided between LSIs.
2. Description of the Prior Art
FIG. 1 shows an example of the arrangement of a conventional open drain type interface circuit.
As shown in FIG. 1, in a conventional open drain type interface circuit, when 3-bit data is to be exchanged between chips A and B, first transistors MN0 to MN2 are arranged for three bus lines B0 to B2, respectively, to drive them. The current flowing in an inductance component L between an internal ground line and an external ground line changes depending on the codes exchanged between the chips A and B. This produces an internal ground potential bounce, resulting in a decrease in noise margin at the interface level.
For example, in the circuit shown in FIG. 1, if the current flowing in each of the bus lines B0 to B2 is represented by I, the current flowing in the inductance component L changes from 0 to 3I in accordance with the codes exchanged between the chips A and B.
More specifically, when all signals x0 to x2 input to the gates of the first transistors MN0 to MN2 are at low level ("0"), all the transistors MN0 to MN2 are set in the OFF state. As a result, a current flowing in the inductance component L is zero. When all the signals x0 to x2 input to the gates of the first transistors MN0 to MN2 are at high level ("1"), all the first transistors MN0 to MN2 are set in the ON state. As a result, a current of 3I flows in the inductance component L.
When, therefore, all the bits of the code exchanged between the chips A and B are inverted, i.e., changed from "000" to "111" or "111" to "000", the current flowing in the inductance component L changes from 0 to 3I or 3I to 0 in a short period of time. As a result, an induced voltage (noise: ground bounce) is produced on the internal ground line owing to a parasitic inductance component.
As a method of solving the above problem, a method of transmitting a 1-bit signal through two differential signal lines is available.
In addition, a low weight coding method has recently been proposed (1996 IEEE Symposium on VLSI Circuit, proceedings: pp. 144-145). In this method, the ratio of "1"s (high level) contained in a binary signal exchanged between LSI interfaces or the ratio of transition of the signal between "0" and "1" is operated by adding a redundant bit, thereby reducing noise or power. Noise can be reduced in half by limiting the number of "1"s contained in an output code to 1/2 or less using this low weight coding method.
In the above conventional interface circuits, the following problems are posed.
(1) In the circuit designed to transmit a 1-bit signal through two differential signal lines, the numbers of signal lines and pins between LSIs increase twice, resulting in an increase in package cost.
(2) In the low weight coding method, changes in current flowing in the inductance component cannot be completely eliminated. To do this, more redundant bits and a more complicated coding circuit are required.